This invention relates generally to semiconductor devices and specifically to an integrated circuit capacitor and a method of forming a capacitor.
The increasing density of integrated circuits (e.g., dynamic random access memories) is increasing the need for materials with high dielectric constants to be used in electrical devices such as capacitors. Generally, capacitance is directly related to the surface area of the electrode in contact with the capacitor dielectric, but is not significantly affected by the electrode volume. The current method generally utilized to achieve higher capacitance per unit area is to increase the surface area/unit area by increasing the topography, such as in trench and stack capacitors using SiO2 or SiO2/Si3N4 as the dielectric. This approach becomes very difficult in terms of manufacturability for devices such as the 256 Mbit and 1 Gbit DRAMs.
An alternative approach is to use a high permittivity dielectric material. Many perovskite, ferroelectric, or high dielectric constant (hereafter abbreviated HDC) materials such as (Ba,Sr)TiO3 (BST) usually have much larger capacitance densities than standard SiO2xe2x80x94SiN4xe2x80x94SiO2 (ONO) capacitors. Various metals and metallic compounds, and typically noble metals such as platinum and conductive oxides such as RuO2, have been proposed as the electrodes for these HDC materials.
As an example, Yamamichi et al. teach a (Ba, Sr) TiO3 (BST) based stacked capacitor with a RuO2/Ru/TiN/TiSix storage node. xe2x80x9cAn ECR MOCVD (Ba,Sr) TiO3 based stacked capacitor technology with RuO2/Ru/TiN/TiSix storage nodes for Gbit-scale DRAMs,xe2x80x9d 1995 IEDM 119. In this process, fully planarized n-type polysilicon plugs were fabricated. Fifty nanometer titanium and 50 nm TiN layers were then deposited using a Ti metal target. This double layer was treated by RTA in N2 at 700xc2x0 C. for 30 seconds to form a TiSix silicide layer. Furthermore, a 50-100 nm metal Ru layer was inserted between the RuO2 and BST deposition.
Unfortunately, the materials which are compatible with HDC dielectrics tend to be difficult to process. For example, Yamamichi et al. teach only a simple block structure of RuO2. Much engineering effort has gone into processing materials such as silicon, oxides and nitrides but less common materials have been the subject of less investigation. Accordingly, techniques to deposit and etch materials other than those commonly used are not well known. As a result, it is presently difficult to use HDC materials in anything but the simplest structures.
The present invention provides an integrated circuit capacitor which can be used in a wide variety of devices including dynamic random access memories (DRAMs). As DRAM dimensions continue to shrink and the density corresponds to increase by factors of four, the storage cell is getting small while the required storage charge remains about the same. Conventional oxynitride (N/O) dielectrics have smaller storage charge per unit area than high dielectric constant materials such as Ta2O5, Ba1-xSrxTiO3 (BST), SrTiO3, and Pb1-xZrxTiO3 (PZT). Thus, metal-insulator-metal (MIM) capacitors using the high dielectric constant materials have been proposed for supplying high storage charge density in a small storage cell. The present invention proposes self-aligned MIM capacitor formation which can be used in conjunction with high dielectric constant materials.
The capacitor formation begins with a base electrode material adjacent an insulating region. This base electrode material can comprise polysilicon or a metal. A layer of a first material, such as a siliciding metal, is formed over the base electrode material as well as the adjacent insulating region. A self-aligned capacitor electrode can then be formed by reacting the first material with the base electrode material and removing unreacted portions of the first material from the insulating region. The capacitor is then completed by forming a dielectric layer over the self-aligned capacitor electrode and a second capacitor electrode over the dielectric layer. Each of the dielectric layer and/or the second capacitor electrode may be aligned with the storage node but do not have to be.
In one specific embodiment, a bottom electrode formed from doped polysilicon is patterned using conventional photoresist and etching. A conformal silicide layer is formed along the bottom electrode (or storage node in a DRAM) through silicidation using rapid thermal anneal (RTA) following a chemical vapor deposition (CVD) metal deposition. The non-silicided metal layer is selectively etched away. A nitridation process using N2 or NH3 plus rapid thermal nitridation (RTN) is applied to form a metal nitride conductive layer along the bottom electrode. During this process, a thin SiON layer may consequently be formed on the surface of any adjacent oxide regions. The dielectric and top plate are sequentially deposited on the bottom electrode to form the self-aligned MIM capacitor.
The resultant structure provides a novel integrated circuit capacitor. In one embodiment, this capacitor includes a semiconductor region, a silicide layer disposed on the semiconductor region, a conductive nitride layer disposed on the silicide layer, a dielectric layer disposed on the silicide layer, and a conductive layer disposed on the dielectric layer. A second embodiment capacitor has a first electrode which includes a semiconductor region and a conductive nitride layer disposed on the semiconductor region. The conductive nitride includes a metal silicide.
The present invention discloses a unique process for forming a self-aligned capacitor plate. In addition, this self-aligned electrode has good oxidation resistance and a high work function. For example, conductive nitride electrodes have better oxidation resistance and higher work function than pure metal electrodes. These conductive nitrides can be used as direct capacitor electrodes or electrode diffusion barriers, which are typically needed for BST or PZT deposition. In particular, this self-aligned conductive nitride electrodes are suitable for the Ta2O5.